Espressif Systems /ESP32-S2 /RTC_CNTL /ANA_CONF

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Interpret as ANA_CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (I2C_RESET_POR_FORCE_PD)I2C_RESET_POR_FORCE_PD 0 (I2C_RESET_POR_FORCE_PU)I2C_RESET_POR_FORCE_PU 0 (GLITCH_RST_EN)GLITCH_RST_EN 0 (SAR_I2C_FORCE_PD)SAR_I2C_FORCE_PD 0 (SAR_I2C_FORCE_PU)SAR_I2C_FORCE_PU 0 (PLLA_FORCE_PD)PLLA_FORCE_PD 0 (PLLA_FORCE_PU)PLLA_FORCE_PU 0 (BBPLL_CAL_SLP_START)BBPLL_CAL_SLP_START 0 (PVTMON_PU)PVTMON_PU 0 (TXRF_I2C_PU)TXRF_I2C_PU 0 (RFRX_PBUS_PU)RFRX_PBUS_PU 0 (CKGEN_I2C_PU)CKGEN_I2C_PU 0 (PLL_I2C_PU)PLL_I2C_PU

Description

Configures the power options for I2C and PLLA

Fields

I2C_RESET_POR_FORCE_PD

SLEEP_I2CPOR force pd

I2C_RESET_POR_FORCE_PU

SLEEP_I2CPOR force pu

GLITCH_RST_EN

Set this bit to enable a reset when the system detects a glitch.

SAR_I2C_FORCE_PD

Sets this bit to FPD the SAR_I2C.

SAR_I2C_FORCE_PU

Sets this bit to FPU the SAR_I2C.

PLLA_FORCE_PD

Sets this bit to FPD the PLLA.

PLLA_FORCE_PU

Sets this bit to FPU the PLLA.

BBPLL_CAL_SLP_START

start BBPLL calibration during sleep

PVTMON_PU

1: PVTMON power up , otherwise power down

TXRF_I2C_PU

1: TXRF_I2C power up , otherwise power down

RFRX_PBUS_PU

1: RFRX_PBUS power up , otherwise power down

CKGEN_I2C_PU

1: CKGEN_I2C power up , otherwise power down

PLL_I2C_PU
  1. PLL_I2C power up ,otherwise power down

Links

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